PCIe study part (1)

PCIe
● topology : Point-to-Point
● frequency: 2.5 GHz
● width : 2 wires per lane/per direction (Up to 32 lanes)
● Max. throughput : 500~16000 MB/sec
● Split transaction : Yes
● Dev. type: Root complex, Switches, Bridges, Endpoints
● Layer : Physical layer, Data Link layer, Transaction layer

● PCIe employs packets to accomplish data transfer between devices--
Transaction Layer Packets (TLPs)

● There are 4 types of transactions--
Memory, I/O, Configuration, Messages

● What is transactionsseries ?
series of packet transmissions to complete information exchange between
requester and completer

● Posted = Requester transmits TLP request packet, completer
does not return completion packet --> Memory Write, Message

● Non-posted = Requester transmits TLP request packet,
completer returns completion packet to requester,
May include data in the request or completion TLP
--> Memory Read, Memory Read Lock, I/O Read, I/O Write, Config Read, Config Write